NASCUG 13 Video Presentations

North American SystemC User's Group

6/13/10

NASCUG 13 brought users together to discuss the newest advancements in sustainable and flexible solutions for ESL design. The presentations below were delivered at the Design Automation Conference (DAC) 2010.

Umesh Sisodia    

How to Create Adaptors Between Modeling Abstraction Levels

Umesh Sisodia, CircuitSutra Technologies Pvt Ltd
View Presentation (16 min.)

This presentation discusses how to create adaptors between various modeling abstraction levels. The SystemC model of an IP has to be created at a specific abstraction level for it to be suitable for a certain use case. There are different abstraction levels possible when creating the SystemC model. Adaptors allow the model created at one abstraction level to be used at another abstraction level, allowing the maximum code reusability and the mixing of models at different abstraction levels in a single virtual platform. This presentation discusses the different aspects of adaptors: what adaptors are, why adaptors are required, how to use adaptors in different scenarios, and how to create the adaptors.

Jiong Ou    

Modeling Communication Systems Using the SystemC AMS Building Block Library

Jiong Ou, Institute of Computer Technology, Vienna University of Technology
View Presentation (16 min.)

Simulation of signal processing systems and communication systems, combined with AMS functions, usually tends to be slow in standard simulation environments as the high frequencies lead to very small time steps and, therefore, many calculations. The SystemC AMS extensions offer modeling in Timed Data Flow (TDF), which allows faster simulations as the scheduling is done in advance. However, the modeling itself still needs a serious investment in time as the system designer has to create most parts of his system from scratch.

In this work, a model-based design approach is developed that provides building blocks for various AMS, RF, and digital functions to ease the design process, relieving the designer from their detailed module implementation and giving him more time to address and analyze the system-level aspects in his design. The implemented building block library, which is compliant with the recently released OSCI SystemC AMS 1.0 standard, focusing on communication and radio frequency systems, in particular on signal sources, modulation/demodulation blocks, filters, measurement, and observation parts. The library components are augmented with the means to specify reconfigurability and the means to model physical implementations of reconfigurability where possible. Another advantage is that the library is available under open source license from the University of Technology Vienna and can be downloaded for free from www.systemc-ams.org.

As an application example, we have built and simulated a SystemC-based OFDM transmitter system by using modules from the AMS building block library. It presents the usage of the library and shows how it can improve the efficiency of designing and modeling communication systems.

Bill Bunton    

Virtual Development Platforms -- What and How Much to Model?

Bill Bunton, LSI Networking Components Division
View Presentation (20 min.)

The SystemC community has developed modeling styles for algorithm development, performance evaluation, virtual system prototypes, and hardware synthesis. A less recognized modeling style is a Virtual Development Platform. Though Virtual Development Platforms have much in common with virtual system prototypes, they have a few unique attributes. First, the Virtual Development Platform is part of an Integrated Development Environment (IDE) used by hardware customers to develop and benchmark their applications. Second, the Virtual Development Platform is maintained as a product for the life of its hardware counterpart. Though the accuracy requirements of Virtual Development Platforms are higher than performance models and virtual prototypes, the accuracy can be refined by back-annotation of performance data and clock counts collected from prototype and production hardware. The model blocks developed as part of a Virtual Development Platform can be used for early performance evaluation and virtual prototypes, but are less useful as a design source for synthesis. This presentation discusses what and how much to model in the context of the Virtual Development Platform developed for the LSI Axxia(tm) family of multi-core communication processors.

John Aynsley    

New Features for Process Control in SystemC

John Aynsley, Doulos Ltd.
View Presentation (33 min.)

A set of extensions to SystemC processes is introduced and explained, including the so-called Process Control Extensions, which allow one process to suspend, resume, or kill another process and permit the specification of multiple synchronous and asynchronous resets. A number of further extensions will be presented that add to the expressive power of SystemC, and the interactions between these extensions and the existing features in SystemC for process control will also be considered and illustrated. The Process Control Extensions themselves were donated to OSCI by Cadence and have been implemented in a beta version of the OSCI proof-of-concept simulator. These and other extensions are currently being considered for inclusion within the SystemC standard by the IEEE P1666 Working Group as part of the re-standardization of SystemC.

Tim Kogel    

Generating Workload Models from TLM-2.0 Based Virtual Platforms for Efficient Architecture Performance Analysis

Tim Kogel, Synopsys, Inc.
View Presentation (24 min.)

SoC architecture definition becomes increasingly challenging as more features are integrated into electronic devices. The Interconnect and Memory Subsystem need to be carefully dimensioned to support the latency and bandwidth requirements of all SoC components under all operating conditions. Today architects can quickly assemble performance models of the envisioned SoC architecture using state-of-the-art SystemC models and tools. The remaining challenge is specification of the workload model representing the communication requirements of the SoC components. Trace-based performance analysis enables this by taking advantage of the observation that up to 80% of the current design is reused in the next generation:

  1. A TLM-2.0 virtual platform of the current design records initiatior transactions with an OS context trace of the software.
  2. The recorded trace is split into separate "threads" representing traffic from different OS processes.
  3. A SystemC-based performance model of the next-generation SoC architecture is built, where the SoC components are represented by trace-based traffic generators.
  4. The trace "threads" are mapped to traffic generators according to the partitioning of the application onto the next-generation SoC.


This case-study presents the results of applying this approach to the TLM-2.0 virtual platform of the ARM Versatile board running an Android software stack.

Mike Meredith    

OSCI and Technical Working Group Update

Mike Meredith, OSCI President
View Presentation (13 min.)

The OSCI and Technical Working Group update can be viewed with the other videos or separately without registration. View now >>

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