Technical Tutorial:
"Cut Your Design Time in Half with Higher Abstraction"

UPFPresented the Design and Verification Conference (DVCon) 2016, this tutorial explains how to use SystemC to write synthesizable models at a higher level of abstraction than RTL.

Part 1: How High-level Synthesis Works: An Intro for Hardware Designers

Frederic Doucet, Qualcomm
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Part 2: The Proposed Accellera SystemC Synthesizable Subset

Mike Meredith, Cadence
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Part 3: High-Level Synthesis and Verification

Peter Frey, Mentor Graphics
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Part 4: HLS in the Wild — Intel's Experience

Bob Condon, Intel
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Part 5: HLS for the FPGA/Programmable Market

Dirk Seynhaeve, Intel
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Part 6: SystemC Synthesis Standard: Which Topics for Next Round?

Frederic Doucet, Qualcomm
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Sponsored By

Cadence Mentor Graphics
Synopsys