SystemC Day 2011 Video Presentations
Co-located at the Design and Verification Conference (DVCon) 2011 on February 29, the second annual SystemC Day brought users together to discuss the newest advancements in sustainable and flexible solutions for ESL design.
Stay tuned for additional presentations from SystemC Day 2011!
Jim Hogan, Vista Ventures LLC, California, USA
SoCs are becoming ubiquitous in semiconductor development. Further, these SoCs are no longer processor-centric, and they are differentiated through the integration of design elements such as multi-CPU, multi-core, DSP cores, hardware accelerators, peripherals and software.
Industry expert and private investor Jim Hogan will discuss the semiconductor industry’s growing adoption of SoC design, and its reliance on diverse sources of hardware and software IP, developed both internally and externally.
After considering recent survey data on both IP and verification drivers, Hogan will discuss the challenges that design and verification teams face for impacted areas such as design assembly and verification.
Complex tool capabilities are required. Many are still nascent, with a handful of companies building out SoC Realization functionality organically and by inorganic growth through acquisition. What can design and development teams do today to drive effective SOC Realization?
John Aynsley, Doulos Ltd., UK
The IEEE SystemC Standard is currently being revised and updated, with the new standard due to be published later in 2011. This new version of the SystemC standard will for the first time include the TLM-1 and TLM-2.0 libraries. Meanwhile, OSCI is working to ensure that the SystemC Proof-of-Concept simulator tracks any changes to the IEEE standard. This presentation will give a concise technical summary of the most important new and revised features in the SystemC standard, will give a behind-the-scenes insight into the rationale behind the changes, and will show examples to illustrate the new features in action.
Cicerone Mihalache, Kotys LLC, USA
Long simulation times have a big impact on the cost and time-to-market of a System on Chip (SoC) due to the iterative nature of the debugging process. SystemC ESL language is used today in all aspects of SoC design (virtual platform, verification, synthesis). Acceleration of SystemC applications is key for increasing the rate of bug fixing. We present a low-cost technique that speeds up a SystemC application on a GNU/Linux platform in direct correlation with the number of CPU cores if certain conditions are met. Low-complexity TLM-2 inter-process adapters split the simulation on multiple GNU/Linux processes, each process running on one core, with minimal modification of the original code of the SystemC application.
TLM Methodology to Enable Architecture Exploration via Co-simulation of SystemC Models with Legacy C/C++ Models
Knute Lingaard (presenter) & Navaneet Kumar (author) FreeScale, USA/India
Early availability of software virtual platform has been a requirement of architects. These virtual platforms are developed by integrating high-fidelity C/C++/SystemC simulation models of individual IP blocks. It's often a challenging task to do a seamless platform integration as these models may not have a common modeling framework.
This paper presents an OSCI TLM-2.0-based methodology to address this model interoperability issue. The methodology has been applied to co-simulate legacy C/C++ models (includes Power cores, Interconnect Fabric, IO devices, DDRC, etc.) together with SystemC-based models (includes DSP cores, DDR target, IO devices, etc.). The legacy C/C++ models, though cycle-accurate, are based on an internal clock-driven simulation framework. They have their own clock management and simulation control mechanism. The paper describes how such legacy models can be made to communicate effectively with SystemC models. The paper also demonstrates how clock determinism and simulation control issues can be resolved between such heterogeneous subsystems during integration.
The work described in this paper has enabled complete re-use of existing C/C++ legacy models and successfully demonstrated quicker platform integration (with SystemC models) without any significant impact on functional and cyclic accuracy of the models.
A Common System Memory Model for SoC Software and Architecture Models using a SystemC/TLM-2.0 Interface
Ali Poursepanj, LSI, NCD System Architecture Group, USA
Systems on a chip (SoCs) generally contain a set of modules (clients) that access a shared memory sub-system (servers) through a memory interconnect (i.e., crossbar). The clients send memory requests to the system memory (servers) while an application is running on the chip.
Architecture models are used to study the performance of the SoCs. Software models are generally used for software development and debugging. Architecture models are time-aware transaction models while software models are register-accurate. Architecture models require accurate memory sub-systems plus representative application workload models. Clients in these models are basically traffic generators that can send traffic to the memory sub-system similar to real applications.
A common memory sub-system implemented in SystemC/TLM-2.0 can be shared by both architecture and software models. In these models, the client traffic generators are initiators and servers are targets. This presentation briefly describes general SoC topologies and how a common memory sub-system implemented in SystemC/TLM-2.0 can be shared by both architecture and software SoC models. These models were implemented and used for architecture analysis and software development at LSI Network Computing Division.
Eric Lish, OSCI Chairman
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