Technical Tutorial:
"UVM Tips and Tricks Plus Preparing for IEEE UVM"

UVMPresented the Design and Verification Conference (DVCon) 2016, this tutorial provides a plethora of tips and tricks to alleviate the struggle of debugging UVM testbenches.

Part 1: UVM Compile Time Tips and Tricks

Doug Perry, Doulos
View PDF


Part 2: UVM Runtime Tips and Tricks

Srivatsa Vasudevan, Synopsys
Slides by Srinivasan Venkataramanan, VerifWorks
View PDF


Part 3: Accellera Standards Update - UVM and IEEE-1800.2

Srivatsa Vasudevan, Synopsys
View PDF (Video not available)


Sponsored By

Cadence Mentor Graphics