"UVM: Ready, Set, Deploy!"
Universal Verification Methodology (UVM) as a standard and an open-source library has been available for more than a year. It continues to gain adoption across the verification community.
This tutorial is presented by expert verification methodology architects and engineers. It begins with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. The tutorial continues with the UVM register package, including how to create and manage stimulus and checking at the register level.
Introduction of these fundamental concepts is followed by four real-life user experiences including lessons learned in preparing transition to UVM, architecting reusable testbenches, debug techniques and use of TLM 2.0 in real verification environments.
This tutorial will appeal to new SystemVerilog users taking their first steps into constrained random verification as well as to power users looking to take advantage of the most recent developments in UVM. Working knowledge of SystemVerilog (IEEE 1800) and familiarity with at least one simulator is assumed.
The tutorial is split into eight parts:
- Part 1: Base Classes in UVM
- Part 2: Communication and Sequences
- Part 3: Customizing Your UVM Environment
- Part 4: Register Modeling in UVM
- User Experience 1: Getting Started with UVM
- User Experience 2: Stacking Verification Components in UVM
- User Experience 3: OVM to UVM Transition
- User Experience 4: VC Building Blocks with UVM