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Accellera Standards Technical Update

Presented at DVCon Europe 2015 on November 11, 2015

Experts in the Accellera standardization give a technical update on the recent standardization activities in the various working groups: Universal Verification Methodology, Portable Stimulus, IP-XACT, and SystemC. Presenters: Uwe Simm, Cadence Design Systems; Sharon Rosenberg, Cadence Design Systems; Erwin de Kock, NXP Semiconductors; Philipp A. Hartmann, Intel.

System-Level Modeling for Today and Tomorrow with SystemC

Presented at DVCon Europe 2015 on November 11, 2015

This presentation starts with an update and overview about recent standardization activities from the different SystemC-related Accellera and IEEE Working Groups, giving a condensed overview about status and plans around SystemC. Presenters: Philipp A Hartmann, Intel; Martin Barnasconi, NXP; Stephan Schulz, Fraunhofer.

The presentation continues with "What is Needed Beyond SystemC and TLM-2.0 for Bigger Systems?" TLM-2.0 is a well-defined abstraction level to model on-chip buses and components that are connected to these buses and interconnects. To enable proliferation of VPs that support as many as possible use cases these off-chip interfaces have to be standardized to enable fast & cheap platform assembly. This presentation addresses the (automotive) use cases and requirements of systems using these off-chip interfaces. Specific scenarios are presented that are used to assess implementation alternatives of such a standard. Finally, some possible solutions for modeling off-chip buses are presented. Presenters: Jérôme Cornet, STMicrolectronics; Martin Schnieringer, Robert Bosch GmbH.

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