NASCUG 11 Video Presentations
North American SystemC User's Group
NASCUG 11 brought together SystemC users and design experts from OSCI Working Groups in an open discussion on the state of SystemC, where it's at, and where it's going. The presentations below were delivered at the Design Automation and Verification Conference (DVCon) 2009.
A Tool for Assertion-Based Verification of TLM Platforms
Luca Ferro, TIMA Laboratory, Grenoble, France
The context of this presentation is the dynamic (i.e., runtime) assertion-based verification (ABV) of TLM SystemC models. In the ABV framework, logic and temporal assertions written in languages such as PSL (Property Specification Language) and SVA are used to capture the design intent. In the last decade, this approach has widely gained acceptance. We present a methodology and a prototype tool named ISIS for checking temporal properties during the SystemC simulation. We especially focus on properties that express constraints on communications (i.e., properties associated with transactional operations); for example: two communication operations with given characteristics must follow each other, data are transferred at the right place, and so on. Those assertions are expressed in the PSL language, including the possibility to use PSL's modeling layer. The ISIS tool performs the automatic construction of the corresponding TLM-oriented monitors, which are linked to the design under verification to check the assertions during simulation. The tool supports timed as well as untimed TLM descriptions and can be used to monitor properties that involve several channels of different types. The properties are specified through a user-friendly GUI.
SystemC-AMS for the Design of Complex Analog/Mixed-signal SoCs
Karsten Einwich, Fraunhofer IIS/EAS, Germany
This presentation shows application areas of the current SystemC-AMS prototype developed by Fraunhofer, using real-life examples of automotive and telecommunication applications used in the industry. Different methods for algorithm design, executable specification, architectural exploration, mixed-signal hardware/software-codesign, and IP protected model exchange are presented. The significant simulation speed-up by using new abstract modeling and simulation approaches for AMS is explained. The seamless integration of TLM and discrete-event models with analog functions is presented, allowing a true multi-domain system-level design and verification method based on SystemC.
Modeling a Virtual MPU
David C Black, XtremeEDA, USA
This talk illustrates a technique used to model software running on an MPU without the use of an ISS. The approach is better than direct execution, because it better separates software from the simulator code and lacks some of the encumbrances of SystemC (the insertion of wait(), for example). The concept can be extended easily to allow for interrupt drivers and time wheel synchronization. The design used TLM-2.0 modeling to create an environment to allow efficient simulation of the hardware. The talk is a fairly technical discussion of an implementation approach used for real customers.
High-speed Packet Router Development in SystemC
William Gnadt, Lockheed Martin MS2, USA
We use SystemC as part of a larger effort to demonstrate the Model-Based System Engineering Method (MSEM). The primary goal of MSEM is to provide unimpeded, undistorted communication between systems, software, and hardware engineers within an engineering team. A secondary goal is to show cost savings, schedule reduction, and risk reduction through model-based design using SystemC. To that end, the techniques applied in MSEM link requirements, hardware architecture, model development, and results. SystemC modeling provides a mechanism to capture hardware functionality into an “executable specification” leading to a design baseline. For this project, MSEM techniques are used for the development of a high-speed packet router using FPGA hardware. The system-level model is designed and captured in SysML, a systems modeling language. System-level requirements are refined into functional modules and flow down to the high-speed packet router. Various hardware architectures are prototyped in SystemC to evaluate alternatives with the lowest parts count. Performance estimates obtained from the SystemC model demonstrate compliance to routing, throughput, and latency requirements. Key conclusions include: accurate prediction of hardware performance using SystemC, application of Rhapsody to support automatic generation of SystemC code and FPGA hardware descriptions, and interfacing a SystemC model with a separate software model for interface verification.