"Case Studies in SystemC"
For more than a decade, SystemC has been used by system architects and design engineers. In more recent times Transaction Level Modeling (TLM2) and virtual prototyping have been an integral part of rewriting some of the models and enhancing the design and verification methodologies from earlier efforts. They have continued to deploy evolving methodologies in new application areas such as radio base station and network processors to bring-up software months ahead of the traditional approach. Other users have attempted to bridge the interoperability gap between SystemC and Universal Verification Methodology (UVM) based on SystemVerilog and other HDLs. In this tutorial, hands-on users and tool developers share their recent experiences and describe advanced methodologies that have helped them achieve significant benefits. A few of the most useful features introduced with SystemC 2.3.0 will be presented and provide code examples that you can take away and start to use for yourself.
The tutorial is split into six sections:
- Part 1: Hints and Tips for Exploiting the Latest Features of SystemC
- Part 2: TLM Use Cases at Ericsson AB
- Part 3: Virtual Prototyping
- Part 4: Efficient Abstractions for AMS System-level Design
- Part 5: Integrating Virtual Platforms with Virtual Prototypes
- Part 6: UVM for SystemC Users