SystemC Day 2010 Video Presentations

2/22/10

Co-located at the Design and Verification Conference (DVCon) 2010 on February 22, the first annual SystemC Day brought users together to discuss the newest advancements in sustainable and flexible solutions for ESL design.

Gary Smith    

Keynote: "ESL: Where We Are and Where We're Going"

Gary Smith, Gary Smith EDA, California, USA
View Presentation (24 min.)

EDA Analyst Gary Smith discusses the long, strange trip of ESL and makes predictions about where the technology and market are headed.

Jack Donovan    

The Metaport: A Technique for Managing Code Complexity

Jack Donovan, HighIP Design, Texas, USA
View Presentation (16 min.)

The metaport is a coding style that can effectively manage code complexity for complex ESL models, especially models that are intended for high-level synthesis. This presentation will give an overview of the metaport concept and dive into the details of a possible implementation.

Herve Alexanian    

OCP socket modeling with TLM-2.0

Hervé Alexanian, Sonics Inc., California, USA
View Presentation (21 min.)

This presentation discusses work performed by the OCP-IP Committee. It introduces a modeling kit based on the TLM-2.0 standard to represent OCP data transfers and covers use models on a spectrum ranging from loosely timed to cycle accurate.

Samuel Goto    

ADL Synthesis using ArchC

Samuel Goto, Master student at UNICAMP
View Presentation (18 min.)

The design and implementation of processors is a complex task. Architecture Description Languages (ADLs) were created to extend existing HDLs, to ease the process of developing and prototyping an architecture by providing a set of tools and algorithms to optimize and automate some of the tedious parts. While much has been done on the specification and business levels of ADLs, there is a huge gap between ADL specifications/simulators and real life processors written in RTL. This project addresses the issues of bringing an ADL description to the RTL level, and reports the development of an extension of ArchC to support this level.

David Black    

Look Ma, No Clocks! Improving Model Performance

David Black, XtremeEDA, Texas, USA
View Presentation (12 min.)

This tutorial-style presentation illustrates some techniques to avoid the inclusion of clocks in SystemC simulations and provide results of simple experiments showing the simulation performance benefits. Concepts discussed include synchronization, clock-free timers, and the effects of clocks on performance. A proposal is made for a simple SystemC class that can simplify coding when clocks are thought to be needed.

Brian Bailey    

TLM-driven Design and Verification Methodology

Brian Bailey, independent consultant
View Presentation (17 min.)

SystemC is well on the road to adoption in a number of areas within the Electronic System Level (ESL) space, but many of those are separated islands today. Virtual Prototyping has seen a huge leap forward with the standardization of TLM 2.0. SystemC is also being used successfully for high-level synthesis at the module level, but to make SystemC pervasive, there must be a link between the applications. In addition, to reap the maximum productivity gains from a migration to a higher-level of abstraction, the verification methodology must also change in significant ways. In this presentation we will explore a new TLM-driven design and verification methodology that is being developed within Cadence, critiqued by their customers and documented in a book, which will be released over a number of months as pieces of it mature.

Eric Lish    

OSCI Technical WG Update

Eric Lish, OSCI Chairman
View Presentation (16 min.)

The OSCI Technical Working Group update can be viewed with the other videos or separately without registration. View now >>

Sponsored By