"Increasing Productivity with SystemC in Complex System Design and Verification"
After a decade of evolution, IEEE 1666, a.k.a. SystemC, is widely used for high-level system design description and verification. As the system complexity increases, SystemC is becoming an enabler to build platforms for advanced design and verification techniques. Some of these techniques include high-level synthesis, virtual platforms for prototyping, and a wide array of debug techniques to locate and isolate hard-to-find bugs. In this tutorial, experienced users and tool developers will share their interdisciplinary use of SystemC in building verification environments that provide early hardware access to software developers.
The tutorial is split into five parts:
- Part 1: Configuration, Control & Inspection Working Group Update
- Part 2: A SystemC Technology Demonstrator using the Xilinx Zynq™-7000
- Part 3: A Unified Design Flow for SystemC Virtual Platforms and High-Level Synthesis
- Part 4: From Virtual Prototyping to RTL Verification
- Part 5: Virtual Prototyping: You don't need a PHD to model in System C and TLM