"SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set"
It’s been 10 years since standardization of SystemVerilog under IEEE 1800. In that time it has experienced tremendous proliferation in the verification world. The language is the heart of UVM reference library and is so well recognized as a necessary driver to verification to efficiency that nearly every company recognizes they need to leverage it to be competitive.
While SystemVerilog introduced many features specific to the verification world, it also introduced many new capabilities for the design world. However, the usage of SystemVerilog in design has been much slower to proliferate in the electronic design industry. The main reason is the large number tools that the design code must successfully navigate on its way to silicon. While SystemVerilog code in the testbench will need to be handled by few tools in the verification space, SystemVerilog in the design must by handled by many tools including synthesis, lint checking, formal, simulation, low power, hardware, equivalence checking, etc. Some will be from multiple vendors, some from point tool providers and some will be home grown tools. Translating the LRM into the working set across multiple tools and vendors takes a mix of planning and testing.
This tutorial brings together leading edge technology users who have used SystemVerilog constructs in their design. They describe their motivations for using SystemVerilog, the success and failures they encountered along the way and the productivity gains achieved.
The tutorial is split into three sections:
- Part 1: Ways Design Engineers Can Benefit from the Use of SystemVerilog Assertions
- Part 2: Experience from Four Years of SVD Adoption
- Part 3: No Excuses for Not Using SystemVerilog in Your Next Design
- Part 4: Panel Discussion