"Software-Driven Verification Using TLM-2.0 Virtual Platforms"
In addition to embedded software development, virtual platforms can effectively be deployed for software-driven verification, in which SystemC TLM-2.0 loosely-timed transaction-level platforms are connected by using transactors to signal-level representations of new subsystem hardware at the RT-level.
This tutorial will provide both a detailed technology overview of software-driven verification techniques using loosely-timed SystemC TLM-2.0 based virtual platforms, and real-world case studies describing how these techniques benefit design teams.
The tutorial is split into five parts:
- Part 1: How We Got Here
- Part 2: Software-Driven Verification Using TLM-2.0 Virtual Platforms
- Part 3: LSI Axxia™ VDP Verification Using SystemC TLM-2.0
- Part 4: Software-Driven Test Environment for TLM-IP Verification
- Part 5: TLM-2.0 Hybrid Virtual Platforms