SystemC SystemC Panel Discussion
DVCon U.S. 2019

At the annual Accellera Luncheon at DVCon U.S. 2019, Laurie Balch from Pedestal Research moderated a SystemC-focused panel that explored what’s next and what should be next for the SystemC standard. Panelists: Stuart Swan, Mentor, A Siemens Business; Filip Thoen, Synopsys, Inc.; Mike Meredith, Cadence Design Systems, Inc.; Mark Glasser, NVIDIA Corp.; and Martin Barnasconi, NXP.


Accellera Standards Technical Update
Presented at DVCon Europe 2015 on November 11, 2015.

Experts in the Accellera standardization give a technical update on the recent standardization activities in the various working groups: Universal Verification Methodology, Portable Stimulus, IP-XACT, and SystemC. Presenters: Uwe Simm, Cadence Design Systems; Sharon Rosenberg, Cadence Design Systems; Erwin de Kock, NXP Semiconductors; Philipp A. Hartmann, Intel.


System-Level Modeling for Today and Tomorrow with SystemC
Presented at DVCon Europe 2015 on November 11, 2015.

This presentation starts with an update and overview about recent standardization activities from the different SystemC-related Accellera and IEEE Working Groups, giving a condensed overview about status and plans around SystemC. Presenters: Philipp A Hartmann, Intel; Martin Barnasconi, NXP; Stephan Schulz, Fraunhofer.

The presentation continues with "What is Needed Beyond SystemC and TLM-2.0 for Bigger Systems?" TLM-2.0 is a well-defined abstraction level to model on-chip buses and components that are connected to these buses and interconnects. To enable proliferation of VPs that support as many as possible use cases these off-chip interfaces have to be standardized to enable fast & cheap platform assembly. This tutorial addresses the (automotive) use cases and requirements of systems using these off-chip interfaces. Specific scenarios are presented that are used to assess implementation alternatives of such a standard. Finally, some possible solutions for modeling off-chip buses are presented. Preseners: Jérôme Cornet, STMicrolectronics; Martin Schnieringer, Robert Bosch GmbH.


Panel Discussion: What is Needed to Drive Design Efficiency?

At the annual Accellera Luncheon at DVCon 2015, invited panelists discussed current practices in design efficiency as well as where standards need to go in order to fill gaps in efficiency.  Moderated by John Aynsley of Doulos. Panelists: Stuart Sutherland, Sutherland HDL; Mike Schaffstein, Qualcomm; Pat Sheridan, Synopsys; Andy Goodrich, Cadence; Bryan Bowyer, Calypto.


Panel Discussion: The Future of Mixed Signal Verification: From Manual Simulations to Full Regression

At the annual Accellera Luncheon at DVCon 2014, invited panelists presented and discussed emerging techniques that would enable the digital-centric mixed-signal community to reach their next level of verification. Moderated by Helene Thibieroz of Synopsys, Inc. Panelists: Scott Little, Intel Corp.; Scott Morrison, Texas Instruments, Inc.; Neyaz Khan, Maxim Integrated; Martin O'Leary, Qualcomm, Inc.


UVM UVM 1.2 Roundtable

At the annual Accellera Breakfast at DAC 2014, John Aynsley, CTO of Doulos, engaged panelists Rich Newton, Ericsson, Amol Bhinge, Freescale, Colin McKellar, Imagination, and Mohamed Elmalaki, Intel in a lively discussion on UVM usage, migration planning and potential future enhancements.

View panelist slides >


Shishpal Rawat, Accellera Systems Initiative Chair, delivers an update on Accellera Systems Initiative activities. Presentation delivered at DAC 2014.


Configuration, Control, and Inspection Working Group Chair Trevor Wieman delivers an update of working group activities at DVCon 2013.


Stan Krolikoski, DVCon 2013 Tutorial Chair discusses Accellera Systems Initiative Day and other happenings at DVCon 2013.


Yatin Trivedi

On the Road to DVCon 2013

Tutorial Chair Yatin Trivedi gives the scoop on the 2013 program. View video >


Shishpal Rawat

Welcome to Accellera Systems Initiative

Shishpal Rawat, Accellera Systems Initiative Chair, talks about the EDA & IP standards organization. View video >